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以FPGA作为实验验证平台,独立地设计能够执行相应指令的MCU内核,整个系统的核心是一个由系统时钟驱动的全局状态机,他控制着所有指令的执行时序。系统内部几乎所有的寄存器都直接与8位的数据总线相连,这种结构使得数据从一个寄存器传输到另一个寄存器只需一个时钟周期,同传统的51核相比减少了传输类指令的时钟周期。加减乘除由不同的逻辑模块完成,这些逻辑模块通过一个交叉阵列开关连接至总线,由指令译码器直接控制交叉开关的连接。测试结果表明在指令的译码以及执行的过程中,各个寄存器和相应总线的数据均符合设计要求。
Taking FPGA as an experimental verification platform, an MCU core capable of executing corresponding instructions is designed independently. The core of the whole system is a global clocked state machine, which controls the execution timing of all the instructions. Almost all registers within the system are directly connected to the 8-bit data bus. This architecture allows data transfers from one register to another to take only one clock cycle, reducing the number of clock cycles . Addition, subtraction, multiplication and division are performed by different logic modules connected to the bus via a cross-bar switch with the direct control of the cross-bar connection by the instruction decoder. The test results show that during the instruction decoding and execution, the data of each register and the corresponding bus meet the design requirements.