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提出了一种雪崩光电二极管(APD)阵列读出电路的系统架构。针对2×8盖革模式InGaAs-APD传感器阵列,进行读出电路系统设计,其中的时间数字转换器(TDC)采用游标卡尺二段式结构,将计数分为粗计数与细计数,计数器放置在像素外,整个芯片共用一个计数器,以实现资源共享,减小了芯片面积,降低了系统功耗。全局采用高、低频时钟分别控制计数、传输数据,进一步降低系统功耗。系统采用CSMC 0.5μm CMOS工艺进行流片验证。测试结果表明,该系统的功能与时序正确。
A system architecture of an avalanche photodiode (APD) array readout circuit is proposed. For 2 × 8 cap Ge-mode InGaAs-APD sensor array, readout circuit system design, including time-to-digital converter (TDC) vernier caliper two-stage structure, the count is divided into rough count and fine count, the counter is placed in the pixel In addition, the entire chip share a counter, in order to achieve resource sharing, reducing the chip area, reducing system power consumption. The overall use of high and low frequency clock control the count, respectively, to transmit data to further reduce system power consumption. The system uses CSMC 0.5μm CMOS process for flow sheet verification. The test results show that the function and timing of the system is correct.