【摘 要】
：
Conventional simulated annealing algorithm for circuit placement suffers from a long run-time problem which is becoming worse with the advance of chip capacity.To deal with this issue,we present the g
【机 构】
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System on Programmable Chip Research Department,Institute of Electronics,Chinese Academy of Sciences
【出 处】
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The 4th International Workshop on Advanced Technologies in P
论文部分内容阅读
Conventional simulated annealing algorithm for circuit placement suffers from a long run-time problem which is becoming worse with the advance of chip capacity.To deal with this issue,we present the generalized dynamic windowing(GDW)technique targeted simulated annealing-based placement on field-programmable gate arrays(FPGAs).In the simulated annealing algorithm,a window is used to control the maximum distance when swapping two circuit blocks,and the range limit of the window is determined by the effective temperature,a control parameter that drops gradually as the annealing proceeds.In the presented GDW,two other factors are applied on the window range limit to accelerate the annealing while maintaining the high quality of final placement.By incorporating the GDW approach in VPR,a state-of-the-art FPGA place and routing tool in academia,our experiment results using a benchmark suit of 20 MCNC circuits demonstrated a 2.4X run-time advantage on average with a penalty of only 2.6%more routed wire length and 3.5%increase in routed critical path delay.
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