The current trend for many application requiring data converters is to get closer and closer to a full SDR(Software Defined Radio)system.While SDR architecture brings many benefits in terms of flexibility and SWaP-C(Size,Weight,Power and Cost)it often translates into higher bandwidth capability and is directly linked to the data converter sampling speed with the Shannon-Nyquist theorem.And this complicates the interface between FPGA(Field Programmable Gate Array)and data converter.Indeed the speed at which FPGA process information is very limited compared to the amount of data generated by high-speed data converter.Of course,this is dealt through massive parallel processing.However transmitting and receiving this huge amount of data has become the system bottleneck as data needs to be transmitted in larger and larger quantities,faster and faster.This paper covers and compares the two means of interfacing at high-speed between FPGA and data converter currently used today: high-speed LVDS parallel interface and high-speed serial interface.It considers multiple aspects ranging from RF with trace length and signal integrity to the system level with cost and ease of development.It starts by introducing these 2 types of interfaces,comparing them and identifying their benefits and drawbacks.Then it discusses the FPGA design of a high-speed parallel interface at 1.5Gbps.It focuses on a transmission from an FPGA to a DAC(Digital to Analog Converter)using the example of an Arria V FPGA from Altera interfacing with an EV12DS460A from e2v.Before concluding,it covers a high-speed serial interface FPGA design at 6Gbps using the ESIstream(Efficient Serial Interface)protocol.It focuses on a transmission from an ADC(Analog to Digital Converter)to an FPGA using the example of an EV12AD500A from e2v interfacing with a Virtex 7 from Xilinx.