In this paper,an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique.
Many current source models CSMs have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade.
The ever-increasing transistor threshold-voltage Vth variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells.To keep power limitations,scaling down
For the last decade,there have been varying techniques for hardware prefetching to improve the system performance.However,untimely prefetching may pollution caches and resulting into significant perfo
A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) during high level synthesis (HL
Soft error rate SER estimation of nano-scale digital integrated circuits is becoming increasingly important since they are getting aggressively vulnerable to soft errors and process variation.
The reclamation and reuse of wastewater is a feasible way to relieve the shortage of freshwater resource. However, the safety of reclaimed water quality is one of the hottest issues, because a large q
Hybrid heterostructures of inorganic and organic semiconductors offer new possibilities for obtaining enhanced functionality by combining the advantageous properties of the individual components,e.g.,