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本文分析了I2C串行总线的数据传输机制,采用硬件描述语言verilog在行为级描述了I2C总线控制器在FPGA上的实现。给出了音频编解码芯片WM8731的配置模块IP核。根据设计流程,对程序进行了前仿真和调试,结果表明符合I2C串行总线的协议要求。并在Quartus II 6.0开发环境下进行了综合,后仿真和下载。
This paper analyzes the I2C serial bus data transmission mechanism, the use of hardware description language verilog described in the behavioral level I2C bus controller on the FPGA implementation. Given the audio codec chip WM8731 configuration module IP core. According to the design flow, the program was pre-emulated and debugged, and the result shows that it meets the protocol requirements of I2C serial bus. And in the Quartus II 6.0 development environment for a comprehensive, post-simulation and download.