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介绍了一种基于双沿输出的14位4 GS/s RF DAC电路设计。该电路采用0.18μm CMOS工艺实现,电路主要包含LVDS接收同步、高速温度计译码器、高速MUX、数据同步电路、DAC核等单元。该电路实现4 GS/s数据率的核心是双沿输出技术。采用该技术只需处理2 GHz时钟,与传统单沿输出DAC相比,时钟频率减少了一半。测试电路能在4 GS/s数据率下正常工作。
A 14-bit 4 GS / s RF DAC circuit design based on dual-edge output is presented. The circuit uses 0.18μm CMOS technology to achieve, the circuit includes LVDS receive synchronization, high-speed thermometer decoder, high-speed MUX, data synchronization circuit, DAC core and other units. The core of the circuit to achieve 4 GS / s data rate is dual-edge output technology. With this technology, which only needs to handle 2 GHz clocks, the clock frequency is reduced by half compared to traditional single-edge output DACs. The test circuit can work normally at 4 GS / s data rate.