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如今,进行高密度专用集成电路(ASICs)的测试绝非易事,有时几乎是不可能的。解决的办法是:使用可测试性设计(DFT),将电路设计和生成测试策略二者同时进行。改变整个的设计和测试过程也许极富挑战性,但从DFT中获得的利益却会远远超过所受的损失。
Testing high-density application-specific integrated circuits (ASICs) today is by no means easy and sometimes almost impossible. The solution is to use a testable design (DFT) to run both circuit design and test strategy generation. Changing the entire design and test process can be challenging, but the benefits of DFT outweigh the losses.