以一款基于HJTC 0.18μm工艺的YAK SOC芯片为例,根据其时钟结构,提出一种能有效减小时钟偏移的方法,该方法通过在门级将时钟根节点分解成若干伪时钟源实现。基于该方法,采用布局布线工具,对YAK SOC芯片进行时钟树综合,得到了较好的效果。给出了一种采用缓冲器和反相器相结合构建时钟树以降低时钟树功耗的方法。通过完成物理设计和功耗分析的数据对比,证明了该优化方法的可行性。 Taking a YAK SOC chip based on the HJTC 0.18μm process as an example, a method of effectively reducing the clock offset is proposed according to the clock structure. The method is implemented by decomposing the clock root node into several pseudo clock sources at the gate level. . Based on this method, the clock tree is synthesized with YAK SOC chip by using the placement and routing tools, and good results are obtained. A method of constructing a clock tree using a combination of a buffer and an inverter to reduce the power consumption of the clock tree is given. By comparing the data of physical design and power analysis, the feasibility of this optimization method is proved.