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提出了一种从E1信号中提取时钟的全数字锁相环。该锁相环结构简单、易于实现、可靠性高,提取的时钟信号的抖动和漂移均满足ITU-T G.823的要求。建立了相位传递数学模型,对电路的原理进行了分析。对该锁相环进行了实验验证,结果表明,在满足ITU-T相关建议的情况下,该电路完全可以从E1信号中提取时钟。
A digital phase-locked loop is proposed which extracts the clock from the E1 signal. The phase-locked loop has the advantages of simple structure, easy implementation and high reliability, and the jitter and drift of the extracted clock signal meet the requirements of ITU-T G.823. The phase transfer mathematical model is established and the principle of the circuit is analyzed. The phase-locked loop was experimentally verified, the results show that in the case of ITU-T recommendations to meet the circumstances, the circuit can extract the clock from the E1 signal.