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研究了不同厚度的超薄栅 1.9nm到 3.0 nm器件在恒压应力下的栅电流变化 .实验结果显示应力诱导漏电流包括两个部分 ,一部分是由界面陷阱辅助隧穿引起的 ,另一部分是氧化物陷阱辅助隧穿引起的 .
The gate current of 1.9nm to 3.0nm ultrathin gate with different thicknesses under constant voltage stress was investigated.The experimental results show that the stress induced leakage current consists of two parts, one is caused by the interface trap assisted tunneling and the other is Oxide traps assist tunneling.