论文部分内容阅读
针对67×67位乘法器,提出并实现新型的设计方法.先提出改进的四阶Booth算法,对乘数编码,以减少部分积的数目,提高压缩速度和减少面积,再研究优化和分配方法,对部分积和进位信号以及一个134位的补偿向量进行优化分配,并对部分积压缩,最后研究K-S加法器的改进方法,求和以实现134位乘积.采用TSMC的0.18μm工艺库,Synopsys的Design compiler工具和Altera的Quautus4.2工具分析结果表明,基于本文方法实现的电路比DesignWare自带的乘法器实现的电路相比,性能总体占优.
For the 67 × 67 multiplier, a new design method is proposed and implemented.An improved fourth-order Booth algorithm is proposed to encode multipliers to reduce the number of partial products, improve the compression speed and reduce the area, and then study the optimization and allocation methods , The partial product of the carry signal and a 134-bit compensation vector to optimize the distribution, and the partial product of the compression, and finally study the KS adder improved method, summing to achieve 134 products using TSMC’s 0.18μm technology library, Synopsys The Design compiler tool and Altera’s Quautus4.2 tools show that the circuit based on this approach achieves better overall performance than the circuit implemented by DesignWare’s own multiplier.