Cycle-based algorithm has very high performance for the simula-tion of synchronous design, but it is confined to synchronous design and it is not as accurate as event-driven algorithm. In this paper, a revised cycle-based algorithm is proposed and implemented in VHDL simulator. Event-driven simulation engine and cycle-based simulation engine have been imbedded in the same simulation environ-ment and can be used to asynchronous design and synchronous design respectively. Thus the simulation performance is improved without losing the flexibility and ac-curacy of event-driven algorithm.