论文部分内容阅读
基于55 nm CMOS工艺,设计了一种宽频带高速锁相环(PLL).PLL中的压控振荡器(VCO)采用8位开关电容阵列和变容管阵列,实现了对VCO振荡频率的调节和不同频段之间的切换.VCO采用分段式结构,实现了8.7～12.5 GHz的宽频率范围.分段结构中,每个频段的频率增益Kvco较低,实现了良好的相位噪声性能.仿真结果表明,在1.2V电源电压下,该PLL的最高工作频率为12.5 GHz,锁定时间为小于2.5μs,相位噪声为-106 dBc·Hz-1@1MHz.“,”A high speed phase locked loop (PLL) circuit with a wide bandwidth was designed in a 55 nm CMOS technology.The voltage-controlled oscillator consisted of an 8 bit switched capacitor array and a varactor array,which was applied to regulate the VCO oscillation frequency and to switch the bands with different frequencies.A segmented structure was used in the VCO to reach a broadband coverage from 8.7 to 12.5 GHz.Because the frequency gain (Kvco) of each frequency band was low in the segmented structure,a nice performance of phase noise was obtained.The simulation results showed that the maximum working frequency of the PLL was 12.5 GHz at a 1.2 V supply,the lock time was less than 2.5 μs,and the phase noise was-106 dBc · Hz-1 at al MHz offset from 12.5 GHz.