RSA加密是一个运算密集的过程 ,为了 CPU能实时进行处理 ,设计了一种嵌入式 RSA处理器 ,它可以在外部微处理器的控制下完成 RSA加解密运算。设计中采用了适合硬件实现的 CIOS方法 ,在保持硬件规模较小的同时加速模乘运算速度。在设计中还采用了窗口法减少模幂运算过程中所需进行的模乘运算次数 ,大大提高了处理速度。在电路的控制逻辑中 ,采取了流水线操作 ,进一步提高了处理速度。在 2 0 MHz的时钟频率下 ,该处理器完成 10 2 4bit的模幂运算最多只需 16 0 ms。电路规模约为 2 6 0 0 0等效逻辑门 ,适合用于各种嵌入式系统中 RSA encryption is a computationally intensive process. In order for the CPU to process in real time, an embedded RSA processor is designed to perform RSA cryptographic operations under the control of an external microprocessor. The design uses a CIOS method suitable for hardware implementation, accelerating the modular multiplication speed while keeping the hardware size small. In the design also uses the window method to reduce the modular exponentiation required in the process of modular multiplication operations, greatly improving the processing speed. In the control logic of the circuit, take the pipeline operation, to further improve the processing speed. At a clock frequency of 20 MHz, the processor performs a modular exponentiation of 10 2 4 bits up to 160 ms. The circuit size is about 2600 equivalent logic gates, suitable for use in a variety of embedded systems