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本文论述了制造可靠的容错微处理机所需的设计方法.这种方法的效用是通过设计具有二次故障工作的电传操作飞行控制处理机来验证.这种设计方法研究 LSI 器件所出现的多故障模式和现用的LSI 电路根据所设计的设备故障率所预测的元件可靠性降低.容错是根据一组从研究 LSI 电路特别是研究微处理机得到的一般准则通过重构来实现的.人们发现当处理机适当分成几小组器件时,要求二次故障工作的容错冗余级使得可靠性级超过两小时内故障概率小于1×10~(-9)的设计目标.这种方法其所以有许多可取之处是由于设计的一组特制的 LSI 电路有三种线路(其应用在下面讲座).上述三种电路包括两种自检检测器和一个专用分割互连电路.
This article discusses the design methods needed to make a reliable fault-tolerant microprocessor that is validated by the design of a telecontrol flight control processor with secondary fault operation.This design approach investigates the presence of LSI devices Multi-fault modes and current LSI circuits reduce component reliability predicted by the device failure rate designed, and fault tolerance is achieved by refactoring based on a set of general guidelines derived from researching LSI circuits, especially research microprocessors. It has been found that when the processor is properly divided into several small groups of devices, fault-tolerant redundancy levels that require secondary fault work make the reliability level exceed the design goal of less than 1 x 10 ~ (-9) in two hours. There are many advantages due to the design of a special LSI circuit has three lines (which are used in the following lecture) .The above three circuits include two kinds of self-test detector and a dedicated split interconnection circuit.