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To solve the bottleneck issue of high-speed routers and switch fabrics technology for current networks, this paper provides a detailed description of how to implement a shared-memory switch fabric for packet routers by Xilinx FPGAs. The switch fabric, coined SL64, has the notable features as follows: (1) Supporting up to 16 OC-48 line cards; (2) Guaranteeing data lossless through robust flow control; (3) Supporting up to eight priorities with one strict priority; (4) Guaranteeing QoS, high throughput and starvation free through scheduling algorithm WF2Q+; (5) Provideing programmable cell length-64 bytes, 72 bytes and 80 bytes are all available for various applications.In addition, common features such as multicast support, protocol agnostic cell based switch, CRC check for cell header and embedded shared memory are also included in our switch fabric SL64.
To solve the bottleneck issue of high-speed routers and switch fabrics technology for current networks, this paper provides a detailed description of how to implement a shared-memory switch fabric for packet routers by Xilinx FPGAs. The switch fabric, coined SL64, has the (2) Supporting data lossless through robust flow control; (3) Supporting up to eight priorities with one strict priority; (4) Guaranteeing QoS, high throughput and starvation free through scheduling algorithm WF2Q +; (5) Provideing programmable cell length-64 bytes, 72 bytes and 80 bytes are all available for various applications. In addition, common features such as multicast support, protocol agnostic cell based switch, CRC check for cell header and embedded shared memory are also included in our switch fabric SL64.