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提出了一种新的获得二级进位跳跃加法器优化方块分配的算法.根据该算法,在确定最坏路径延时的前提下,首先获得该延时下加法器最大的优化方块尺寸,然后确定任意位二级进位跳跃加法器的优化方块尺寸.优化方块分配的进位跳跃加法器可以缩短关键路径的延时.给出了加法器门级延时、复杂度的分析,分析结果显示,通过优化方块分配,可以以较少的额外门电路获得快速的进位跳跃加法器.该加法器已用PSPICE仿真工具进行了功能验证和仿真.PSPICE仿真分析表明,所提出的二级优化方块分配进位跳跃加法器的速度优于等尺寸二级进位跳跃加法器.
A new algorithm to obtain the optimal block allocation of two-run-in-carry adder is proposed.According to the algorithm, the maximum block size of the adder under the delay is first obtained on the premise of determining the worst-case delay, and then the Optimized block size of arbitrary binary jump adder The optimization of the carry-skip adder of block assignment can shorten the delay of critical path.Analysis of delay and complexity of adder gate is given.The analysis results show that by optimization The block allocation allows a fast carry-skip adder with fewer additional gates, which has been validated and simulated with the PSPICE simulation tool.PSPICE simulation analysis shows that the proposed two-level optimization block allocates carry-skip addition The speed of the device is better than the second-order carry jump adder of equal size.