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本文介绍由CIMI-SUPAERO公司根据两种不同工艺设计的CMOS APS(有源像元敏感器Active Pixel Sensor的缩写——译注)成像器的实验结果。无论采用光电MOS(金属-氧化物-半导体)构成像元,还是采用光电二极管构成像元,两种设计都已完成。第一种电路采用标准的CMOSDLP/DLM(互补型金氧半导体晶体管-双层多晶硅/双层金属)1.2μm工艺设计。这种工艺源于奥地利微系统公司。探测器阵列包括32×32个方形像元,像元间距为50μm。光电二极管(PD)结构,填充系数为75%;光电MOS(PM)结构,填充系数为50%。电路包括行与列地址译码器,还带有读出电路,以便在芯片上完成相关双增量采样,减小列与列之间的固定图案噪声。另外两种芯片采用标准的CMOSSLP(单层多晶硅)/DLM工艺制作,这种工艺源于MIETEC公司,设计的特征尺寸为0.7μm,它包括一个128×128像元阵列,像元间距为21μm,带有模拟读出电路。利用这两种工艺的10个不同阵列器件中没有发现一个不合格品。本文中我们根据暗电流、量子效率、转换增益、动态范围、线性度及空间均匀性等特性,比较了 32×32像元与128×128像元的性能。
This article presents the experimental results of CMOS APS (Active Pixel Sensor Abbreviation) imager designed by CIMI-SUPAERO according to two different processes. Both the design is done whether using a photo MOS (metal-oxide-semiconductor) pixel or a photodiode pixel. The first circuit uses a standard CMOSDLP / DLM (Complementary Metal Oxide Semiconductor Transistor - Double Layer Polycrystalline / Double Metal) 1.2μm process design. This process originates from Austrian Microsystems. The detector array includes 32 × 32 square pixels with a pixel pitch of 50 μm. Photodiode (PD) structure with a fill factor of 75% and a photoelectric MOS (PM) structure with a fill factor of 50%. Circuit includes a row address and a column decoder, also with a readout circuit, in order to complete the incremental correlated double sampling on the chip, reducing the fixed pattern noise between rows and columns. The other two chips are fabricated using a standard CMOS SLP (single-layer polysilicon) / DLM process from MIETEC with a feature size of 0.7μm and a 128 × 128 pixel array with 21μm pixel spacing. With analog readout circuit. No one defective was found in 10 different array devices using these two processes. We herein according to the characteristics of dark current, quantum efficiency, conversion gain, dynamic range, linearity and uniformity of the space, comparing the performance of the 32 × 32 pixels to 128 × 128 picture elements.