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CMOS集成电路在实际的应用中会出现一些问题,问题主要表现在闩锁效应上,闩锁效应已经成为CMOS集成电路正常运作的障碍。特别是随着器件的特征尺码越来越小,这种问题日益突出。本文以P阱CMOS反相器的研究为出发点,探讨CMOS集成电路的工艺结构,并且在此基础上运用可控硅等效电路模型进行分析。通过这些来分析闩锁效应产生的机制和原因,进而探索出闩锁效应产生的3个诱因。从这3个原因出发,然后探讨出抑制闩锁效应的几个措施,这些措施主要是从版图设计和工艺设计方面出发研究出来的。
CMOS integrated circuits in the actual application of some problems, the main problems in the latch-up effect, the latch-up effect has become the normal operation of CMOS integrated circuit barrier. In particular, as the feature size of the device gets smaller and smaller, this problem becomes increasingly prominent. Based on the research of P-well CMOS inverters, this paper discusses the process structure of CMOS integrated circuits, and based on this, analyzes the equivalent circuit model of SCR. Through these to analyze the mechanism and cause of the latch-up effect, and then explore the latch-up effect of the three incentives. Starting from these three reasons, we then explore several measures to suppress the latch-up effect. These measures are mainly based on the layout design and process design.