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提出了一种由锁频环(FLL)和初相角锁相环(PLL)构成的新型三相PLL。FLL采用了一种新型的微分算法来检测频率误差,可避免由电压相角或幅值突变导致的频率检测误差。该新型PLL采用频率自适应数字滤波器(FADF)滤除输入信号中的谐波和噪声,提高了相角的检测精度。FADF利用多重化延时信号消除算法消除频率较低的谐波,然后通过巴特沃斯低通滤波器滤除高次谐波和噪声,可以在dq域准确、迅速地提取基波正序电压。同时,初相角PLL拥有较高的特征频率,使得新型PLL可以在相角突变后迅速地实现同步。通过仿真和实验对新型PLL的性能进行了验证,且为了适用于计算能力较差的控制器,给出了新型PLL的简化方案。
A novel three-phase PLL consisting of a frequency-locked loop (FLL) and an initial phase-locked loop (PLL) is proposed. FLL uses a new type of differential algorithm to detect frequency errors and avoids frequency detection errors due to voltage phase angle or amplitude abrupt changes. The new PLL uses a frequency adaptive digital filter (FADF) to filter out harmonics and noise in the input signal, improving phase angle detection accuracy. FADF uses multiple delayed signal cancellation algorithms to eliminate lower frequency harmonics and then filters higher harmonics and noise through a Butterworth low-pass filter to extract the fundamental positive sequence voltage accurately and quickly in the dq domain. At the same time, the initial phase angle PLL has a high characteristic frequency, making the new PLL can quickly achieve synchronization after the phase angle mutation. The performance of the new PLL is verified through simulation and experiment, and a simplified scheme of the new PLL is given for the controller with poor computing ability.