文中介绍了一种六级 1 2位 1 0 Msample/ s CMOS流水线 A/ D转换器的设计。该设计方案采用了双差分动态比较器结构 ,保证了处理模拟信号的精度与速度 ;采用冗余编码技术 ,进行数字误差校正 ,减小了多种误差敏感性 ,避免了由于余量电压超限而导致的失码 ,并降低了采样 /保持电路和 D/ A转换电路的设计难度。 This paper presents a six 12-bit 1 0 Msample / s CMOS pipeline A / D converter design. The design uses a double differential dynamic comparator structure to ensure the accuracy and speed of processing analog signals; the use of redundant encoding technology for digital error correction, reducing a variety of error-sensitivity, to avoid the margin voltage overrun Resulting in missing codes and reducing the design difficulty of sample / hold circuits and D / A conversion circuits.