介绍了一种新的低功率多米诺 CMOS 逻辑电路,其功率特性基于一种低电压漂移技术。为了减小它的输出电压漂移,对该多米诺门电路的输出变流器进行了改动。结果使其动态电压耗散节省高达36%,同时提高了功率延迟结果。为了达到功率节省和速度间的折衷,采用了一种产生电压漂移可变值的技术,实验结果清楚地显示了所提出的技术在低功率工作时的可行性。参12 A new low power domino CMOS logic circuit is introduced, whose power characteristics are based on a low voltage drift technique. To reduce its output voltage drift, the output converter of the domino gate has been modified. The result is up to 36% savings in dynamic voltage dissipation while improving power delay results. In order to achieve a trade-off between power savings and speed, a technique that produces a variable voltage drift is used and the experimental results clearly demonstrate the viability of the proposed technique for low-power operation. Participation 12