设计继电器逻辑线路,通常是用一边分析,一边作图,随时增加继电器及其触头的方法完成草图设计。用这样的方法设计线路有以下缺点: (1)设计程序不固定,初学者难于掌握; (2)需要反复修改草图,设计速度慢; (3)设计质量完全取决于设计人员的经验和技巧; (4)不易使线路最简单。 Relay logic design circuit, usually with one side of the analysis, while mapping, at any time to increase the relay and contact method to complete the sketch design. The design of the circuit in this way has the following disadvantages: (1) the design process is not fixed, and it is difficult for beginners to master; (2) the sketch needs to be modified repeatedly and the design speed is slow; (3) the design quality depends entirely on the designer’s experience and skills; (4) is not easy to make the line the simplest.