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并发差错检测是提高数字电路与系统可信性的重要技术．文中建立了一种基本并发差错检测电路的结构模型，它由实现电路基本功能的基本功能模块和实现电路并发差错检测功能的检测器两部分级联所构成；提出了表征基于部分自校验概念的并发差错检测机制的一组新概念：精简强故障保险、精简强变量分离、精简强自校验、ｋ容错精简强故障保险、ｋ容错精简强变量分离和ｋ容错精简强自校验，并研究了数字电路并发差错检测的主要概念之间的关系；证明了用基本功能模块与检测器互连，以构造具有不同并发差错检测特性的基本电路所需满足的条件
Concurrent error detection is an important technique to improve the reliability of digital circuits and systems. This paper establishes a basic concurrency error detection circuit structure model, which consists of the basic functions of the basic functions of the circuit module and the implementation of circuit error detection function of the detector cascaded two parts; proposed characterization based on part of the concept of self-calibration A set of new concepts of concurrent error detection mechanism: streamlined and strong fault insurance, streamlined and strong variable separation, streamlined and strong self-checking, k fault-tolerant streamlined fault insurance, k fault-tolerant streamlined strong variable separation and k fault-tolerant The relationship between the main concepts of digital circuit concurrency error detection has been examined and the conditions to be met for interconnection of basic functional modules with detectors to construct a basic circuit with different concurrency error detection characteristics have been demonstrated