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提出了一个用于 SPICE模拟高频互连效应的 RLC互连电路模型 ,该模型考虑了频率对互连电感、电阻的影响 ,适用于从芯片间互连到芯片内互连高频效应的分析。基于所提出的互连模型 ,对频率达 1 0 0 0 MHz时芯片内长互连线的延迟、串扰、过冲等互连寄生效应进行了分析 ,并指出了抑制互连效应的技术途径
An RLC interconnection model for SPICE simulation of high frequency interconnection is proposed. The model considers the effect of frequency on the inductance and resistance of interconnects. It is suitable for the analysis of high frequency effects from inter-chip interconnects to on-chip interconnects . Based on the proposed interconnection model, the interconnection parasitics such as delay, crosstalk and overshoot of the long interconnects in the chip with the frequency up to 100 MHz are analyzed, and the technical approaches to suppress the interconnection effect are pointed out