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数字电视地面广播传输系统标准中的前向纠错编码(FEC),是由BCH码和LPDC码级联组成,其中BCH为外码,LDPC码为内码。以0.4、0.6、0.8这三种码率为研究对象,主要研究LDPC编码器的设计及其FPGA实现,标准中的LDPC码是一种准循环LDPC码。LDPC码的生产矩阵是通过子矩阵的循环移位得到的,为了便于存储把循环移位得到的矩阵存储到ROM中。然后通过Virtex-4芯片,利用ISE仿真平台进行了测试、综合、仿真并得到综合报告,通过与计算机仿真结果进行比较,验证其设计正确性。
The forward error correction coding (FEC) in the standard of digital television terrestrial broadcasting transmission system is composed of concatenation of BCH code and LPDC code, where BCH is outer code and LDPC code is inner code. To 0.4,0.6,0.8 these three code rates for the study, the main study LDPC encoder design and FPGA implementation, the standard LDPC code is a quasi-cyclic LDPC code. The production matrix of the LDPC code is obtained by cyclic shift of the sub-matrix, and the matrix obtained by the cyclic shift is stored in the ROM in order to facilitate storage. Then, the Virtex-4 chip is used to test, synthesize, simulate and get a comprehensive report by using the ISE simulation platform. The comparison with the computer simulation results verifies the correctness of the design.