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研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性,包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性,分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起,同时还有电子的翻越和渗透.在电压应力下,SiO2中形成的缺陷不仅降低了SiO2的势垒高度,而且等效减小了SiO2的厚度(势垒宽度).另外,每一个缺陷都会形成一个导电通道,这些导电通道的形成增大了栅电流,导致器件性能的退化,同时栅击穿时间变长.
The breakdown characteristics of the n-MOSFET with a gate oxide thickness of 1.4 nm at 90 nm were investigated, including the device gate current model under V-ramp stress and the TDDB under CVS (constant voltage stress) ) Characteristics, the device failure and degradation mechanism under voltage stress is analyzed, and it is found that the gate current of the device is not caused by a single tunneling, but also the electron crossover and penetration. Under voltage stress, the defects formed in SiO2 not only reduce SiO 2 barrier height and equivalently reduces the thickness of SiO 2 (barrier width) .In addition, each defect forms a conductive path that increases the gate current, resulting in degradation of device performance, Grid breakdown time becomes longer.