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提出了一种基于确定性测试集的数字集成电路随机测试生成方法。通过将完备测试集分成若干子集 ,由每一子集计算产生子集中测试矢量的被测电路各主输入端取“1”值的概率组合即所谓的权集。通过减小测试子集生成概率的方差可以减少低生成概率的测试矢量数 ,进而减小在高故障覆盖率下的测试长度 ,该方法对大规模集成电路的内测试和外测试皆适用
A method of random test generation for digital integrated circuits based on deterministic test set is proposed. By dividing the complete test set into several subsets, the probability combination of taking “1” value of each main input terminal of the circuit under test generating the test vectors in the subset is calculated by each subset, that is, the so-called set of weights. By reducing the variance of the test subset generation probabilities, the number of test vectors with low probability of generation can be reduced and the test length at high fault coverage can be reduced. This method is suitable for both internal test and external test of large scale integrated circuits