为研究槽缝型缺陷参考平面对高速信号的影响,主要基于场路混合仿真,使用三维全波方法提取槽缝缺陷参考平面参数,并结合电路仿真,分别对单端微带线与耦合微带线跨越不连续参考平面的影响进行分析,讨论了这些影响是如何作用于高速数字系统的时序与噪声,并引入眼图予以说明。仿真结果表明开槽长度与宽度都会增大信号回路电感,信号上升沿时间会随着返回路径的增加而退化,从而引起高速数字系统时序抖动,耦合微带线间的串扰随返回路径增加而急剧增加,在抖动与噪声的共同作用下,会对系统数据接收到的信号产生破坏性作用,在高速PCB设计中应遵从使返回路径最小的原则,避免共同的信号返回路径是关键。由此总结出降低不完整参考平面高速互连线间耦合及串扰的设计规则。 In order to study the effect of slot reference plane on high-speed signal, a 3D full-wave method is used to extract the reference plane parameters of slot defects based on the field-based mixed simulation. Combined with the circuit simulation, The effect of the line crossing the discontinuous reference plane is analyzed, and the timing and noise of the effects on the high-speed digital system are discussed and introduced into the eye diagram. The simulation results show that the slot length and width increase the inductance of the signal loop. The rising edge time of the signal degrades with the increase of the return path, causing high-speed digital system timing jittering. The crosstalk between coupled microstrip lines increases sharply with the return path The combination of jitter and noise can have a devastating effect on the signals received by the system data. The principle of minimizing the return path should be followed in high-speed PCB design. It is crucial to avoid the common signal return path. Therefore, the design rules for reducing the coupling and crosstalk between high-speed interconnect lines of incomplete reference planes are summarized.