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信息安全领域中,单向散列函数SHA-1是常用的认证算法之一。本设计的目的是要用FPGA高速实现SHA-1。设计主要分为控制模块和运算模块。控制模块部分采用计数器集中控制方式,占用资源少,时效性好。运算模块的部分延时最大的是5×32连加器部分,它设计的好坏直接影响到整个芯片的速度。对此,本设计采用了进位保存加法器(CSA),大大提高了芯片速度。本设计是在Quatus_4.2运行环境下采用VHDL语言编程实现。
In the field of information security, one-way hash function SHA-1 is one of the commonly used authentication algorithms. The purpose of this design is to implement SHA-1 at high speed with FPGA. Design is divided into control modules and computing modules. Part of the control module using counter centralized control mode, less resource consumption, good timeliness. Part of the computing module delay is the largest part of 5 × 32 with the adder, it is a direct impact on the design of the entire chip speed. In this regard, the design uses a carry-save adder (CSA), greatly improving the chip speed. The design is in the Quatus_4.2 operating environment using VHDL language programming.