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本文介绍应用双层多晶硅和NMOS/CMOS工艺设计具有典型存取时间为80ns的全静态RAM。该存储器工作和保持方式中功耗分别为300mw和75mw。 该RAM采用了具有N~+掺杂多晶硅栅的N型和P型MOS晶体管的N阱CMOS工艺。通过两步扩散工艺,避免了在形成源漏区的硼离子注入工序中硼掺杂到P型晶体管的硅栅中去,其结果避免了硼穿透400(?)(?)的薄栅氧化层引起P型晶体管的阈值电压漂移的问题。存储单元是在P型衬底上用NMOS工艺制作。外围电路,例如行和列译码器,输入/输出电路及读出放大器等由N阱CMOS形成。
This article describes the application of double-layer polysilicon and NMOS / CMOS process design with a typical access time of 80ns full static RAM. The memory work and maintain power consumption were 300mw and 75mw. The RAM uses an N-well CMOS process with N + and P-type MOS transistors with N + doped polysilicon gates. Through the two-step diffusion process, boron is prevented from being doped into the gate of the P-type transistor in the boron ion implantation process for forming source and drain regions, and as a result, the thin gate oxidation of boron (400)? Layer causes the threshold voltage shift of the P-type transistor. The memory cell is fabricated on a P-type substrate using an NMOS process. Peripheral circuits such as row and column decoders, input / output circuits, sense amplifiers, and the like are formed of N-well CMOS.