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设计了一种用于电荷泵锁相环(CPPLL)快速锁定的动态鉴频鉴相器(PFD)。该PFD采用传统结构,利用开关延时动态D触发器预充电,复位时间内输入时钟边沿未发生丢失,有效地消除了盲区。基于TSMC 0.18μm CMOS工艺,用Cadence Spectre对其进行仿真验证。结果显示,采用新型PFD的锁相环,其锁定速度提高40.3%,频率范围达1 MHz~2 GHz。
A dynamic phase frequency detector (PFD) for fast-locking charge pump phase locked loop (CPPLL) was designed. The PFD adopts the traditional structure and pre-charges with the dynamic D flip-flop with the switch delay. The input clock edge does not lose during the reset time, effectively eliminating the dead zone. Based on the TSMC 0.18μm CMOS process, it is verified with Cadence Specter. The results show that the new PFD PLL, the lock speed increased 40.3%, the frequency range of 1 MHz ~ 2 GHz.