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最近,美帝宇宙航行局经研究认为 MOS 集成电路的20%～40%的缺陷是由过量电压和氧化物中存在缺陷而引起的,其结果导致栅极的短路和漏电流的增加。由栅导体电击穿引起的栅短路,使 MOS 晶体管及集成电路的成品率和可靠性都存在问题。在防止过量电压的 MOS 器件的栅极保护方面,过去广泛使用的是 J·莱兰特·赛里的方法,把 PN 结与栅极并列放置,向 PN 结施加反向偏压而使晶体管工作。
Recently, the Aerospace Agency of the United States of America has considered that 20% to 40% of the defects in MOS integrated circuits are caused by excess voltage and defects in the oxide, resulting in an increase in the gate short circuit and leakage current. The gate short circuit caused by the electrical breakdown of the gate conductor poses problems with the yield and the reliability of the MOS transistor and the integrated circuit. In the past, the gate protection of MOS devices against overvoltages was widely used in the past by the method of J. Reilanter Race, placing the PN junction in parallel with the gate and applying a reverse bias to the PN junction to turn on the transistor .