A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

来源 :Journal of Semiconductors | 被引量 : 0次 | 上传用户:talygs
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This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation(WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator(VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 m CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications. This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase / quadrature-phase (I / Q) signal over a frequency range of 220-1100 MHz for wireless networks of industrial automation (WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4-2.2 GHz ultralow gain voltage-controlled oscillator (VCO) is adopted by 128 tuning curves. Second, a selectable I / Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is shorten settling time. With a 200 The peak measured phase noise is 106 dBc / Hz at a 10 k Hz offset and 131 dBc / Hz at a 1 MHz offset. In the TSMC 0.18 m CMOS process, the synthesizer occupies a chip area of ​​1.2 mm2, consumes only 15 m W from the 1.8 V power supply, and settles within 1 3.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.
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