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;Oversampling sigma-delta (∑-△) analog-to-digital converters (ADCs) are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,the ∑-/△ ADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entire ∑-△ ADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB (cascade-of-integrators feed-back) structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72 × 0.75 mm2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits (ENOB) was almost 18-bit.