Actel公司是新型可编程逻辑方案的供货商,他们为现场可编程门数组(FPGA)的开发和设计推出了优化的下一代集成设计环境Libero。新版本Libero支持混合模式设计输入,设计师可以选择高级VHDL或Verilog HDL语言模块与原理图模块混合。这种混合模式可以使设计师用原理图描述述HDL中的复杂功能,或将那些模块组合在一起。这种新功能有利于将知识产权(IP)集成到复杂FPGA,并能缩短产品面市时间,提高产量。 Actel Corporation is a supplier of new programmable logic solutions that unveiled Libero, the next-generation, integrated design environment for the development and design of field-programmable gate arrays (FPGAs). The new version of Libero supports mixed mode design input, designers can choose advanced VHDL or Verilog HDL language module mixed with the schematic module. This hybrid approach allows designers to use schematic diagrams to describe complex functions in HDL, or to combine those modules together. This new feature facilitates the integration of intellectual property (IP) into complex FPGAs and shortens time-to-market and increases production.