图1a所示硬件反位和线性地址发生器将时域数字N取样的记录进行反排。这种电路的基本作用是在形成实时蝶形FFT前,将数据倒排,并按以前发表在EDN设计思路栏中文章行事(DAC和μP实施硬件窗口发生器,1994年3月31日号第58页)。图1(a)只表示了潜在地址范围的一档。对16位以上的记录,简单的解决办法是级联多个记数器和加多个乘法器。诀窍在于产生正常二进位正数的对应影像,如图1(b) The hardware anti-bit and linear address generator shown in Figure 1a inverts the time-domain digital N-sample records. The basic function of this circuit is to invert the data before forming a real-time butterfly FFT and act as previously published in the EDN Design Ideas section (DAC and μP Implement Hardware Window Generator, March 31, 1994 58 pages). Figure 1 (a) shows only the first file of the potential address range. For more than 16 records, a simple solution is to cascade multiple registers and add multiple multipliers. The trick is to produce a normal binary positive corresponding image, as shown in Figure 1 (b)