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本文主要介绍了通过步进式光刻、反相剥离和F基等离子体刻蚀工艺在晶元级Si衬底上制备SiO_2图形的过程,在6 in(15.24 cm)Si衬底上实现了均匀的周期分别为1.0μm和1.6μm、深宽比分别为2.3和1.4的SiO_2周期性掩膜.尤其在周期为1μm的条件下,窗口通过过曝光和反相剥离工艺减小到330 nm,该尺寸超越了试验用步进式光刻设备的极限精度尺寸.在通过HF和KOH溶液处理后,得到了带有V型槽和较光滑侧壁的SiO图形的Si衬底,该图形适用于Ⅲ-Ⅴ半导体通过深宽比位错捕获技术的材料生长.这种均匀的晶元级图案制备方案促进了图形化Si衬底技术和Si基Ⅲ-Ⅴ半导体异质外延.
This paper mainly introduces the process of preparing SiO 2 pattern on Si substrate by means of stepper lithography, reverse-phase stripping and F-based plasma etching, and achieves uniform on 6 in (15.24 cm) Si substrate With periodicity of 1.0μm and 1.6μm, respectively, with aspect ratio of 2.3 and 1.4, respectively.With the period of 1μm, the window is reduced to 330 nm by over-exposure and reverse-phase-stripping process, The dimensions exceeded the limit precision dimensions of the experimental stepper lithographic apparatus.After processing with HF and KOH solutions, a Si substrate with a V-shaped groove and smoother sidewalls of SiO pattern was obtained which is suitable for use in III -V semiconductors are grown by the material of aspect-ratio dislocation capture technique This uniform wafer level patterning scheme facilitates the patterned Si substrate technology and Si-based III-V semiconductor heteroepitaxy.