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片上网络(network on chip,NoC)作为一种全新的片上互连通信架构,面积受限,却具有丰富的线资源。而且,三维片上网络的层间互连线很短,同时提供了在第三维度上的互连扩展性。根据这些特性,该文提出了一种基于三维Mesh片上网络的双链路互连架构。在垂直方向上,该架构采用双链路互连,使其通信带宽加倍;而且,跨层连接的垂直链路降低了消息传输的路由跳数。这些都带来网络平均延时的降低和最大吞吐量的提高,却仅仅增加一些控制逻辑电路。仿真结果验证了理论分析。与传统的单链路架构相比,该架构以较小的面积开销换取了较大的性能提高。
Network on chip (NoC), as a new kind of on-chip interconnection communication architecture, has limited area and rich line resources. Moreover, the inter-layer interconnection lines of the three-dimensional on-chip network are short while providing the interconnection scalability in the third dimension. According to these characteristics, this paper proposes a dual-link interconnect architecture based on three-dimensional Mesh on-chip network. In the vertical direction, the architecture uses dual-link interconnects to double their communications bandwidth; moreover, the vertical links across the layers reduce the number of hops for message transmission. All these bring about the average delay of the network is reduced and the maximum throughput is improved, but only increase some control logic circuits. Simulation results verify the theoretical analysis. Compared with the traditional single-link architecture, the architecture in exchange for a smaller area for greater performance gains.