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This paper presents a 10-bit 50-MS/s subrange successive-approximation register(SAR) analog-todigital converter(ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC.In the coarse ADC,multicomparator SAR architecture is used to reduce the digital logic propagation delay,and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC.With that combination,power dissipation also can be much reduced.Meanwhile,a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques,such as splitting capacitors array,are borrowed to reduce the power consumption.Fabricated with 1P8 M 130-nm CMOS technology,the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio(SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply,resulting in a figure of merit(FOM)of 12 fJ/conversion-step.The core area is only 0.045 mm~2.
This paper presents a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, a 10-bit 50-MS / s subrange successive-approximation register (SAR) Multicomparator SAR architecture is used to reduce the digital logic propagation delay, and a conventional SAR ADC with monotonic switching method is used as the fine ADC. This combination, power dissipation also can be much reduced. adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabrication with 1P8 M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS / s with 1-Vsupply, resulting in a figure of merit (FOM) of 12 fJ / conversion-step.The core area is only 0.045 mm ~ 2.