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在信息技术设备系统的大规模集成电路(LSI)中,“要求工作中的功率消耗极小”是一个重要课题。为降低LSI的工作电压,有效的方法是降低电源电压。迄今的目标是指向IV水平,力图实现低电压化。但是考虑到低于1V时,CMOS(互补型金属氧化物半导体)电路的性能会显著劣化,难于达到实用化。即使按国际上半导体技术的发展方针,今后5年期间,电源电压的进展也仅保持在1V左右。
In large scale integrated circuits (LSIs) for information technology equipment systems, “requiring very little power consumption at work” is an important issue. In order to reduce the working voltage of LSI, it is effective to reduce the mains voltage. So far the goal is to point to the level of IV, trying to achieve low voltage. However, when it is considered that the performance of a CMOS (Complementary Metal Oxide Semiconductor) circuit is significantly deteriorated below 1 V, it is difficult to put it into practical use. Even in accordance with the international semiconductor technology development guidelines, the next five years, the progress of the supply voltage is only maintained at about 1V.