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A dual-loop phase-locked loop(PLL)for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator(VCO)gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.
A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. The PLL is fabricated in a Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of -99 dBc / Hz @ 1 MHz offset from a 5.5 GHz carrier.