论文部分内容阅读
This paper presents a low-power small-area digitally controlled oscillator(DCO) using an inverters interlaced cascaded delay cell(IICDC).It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse-tuning stage of the DCO uses IICDC,which is power and area efficient with low phase noise,as compared with conventional delay cells.The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2.The output frequency range is 140–600MHz at the power supply of 1.8V.The power consumption is 2.34m W @ a 200MHz output.
This paper presents a low-power small-area digitally controlled oscillator (DCO) using an inverters interlaced cascaded delay cell (IICDC). It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse- tuning stage of the DCO uses IICDC, which is power and area efficient with low phase noise, as compared with conventional delay cells. The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2. output frequency range is 140-600MHz at the power supply of 1.8V. The power consumption is 2.34m W @ a 200MHz output.