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描述了一种用综合性方法设计的亚 5 0 nm自对准双栅 MOSFET,该结构能够在改进的主流 CMOS技术上实现 .在这种方法下 ,由于各种因素的影响 ,双栅器件的栅长、硅岛厚度呈现出不同的缩减限制 .同时 ,侧面绝缘层在器件漏电流和电路速度上表现出特有的宽度效应 .建立了关于这种效应的模型 ,并提供了相关的设计指导 .另外 ,还讨论了一种新型的沟道掺杂设计 ,命名为 SCD.利用 SCD的 DG器件能够在体反模式和阈值控制间取得较好的平衡 .最后 ,总结了制作一个 SADG MOSFET的指导原则
A sub-50 nm self-aligned double-gate MOSFET designed in a comprehensive way is described, which can be implemented in a modified mainstream CMOS technology. Due to various factors, the dual-gate device Gate length and the thickness of silicon island exhibit different reduction limits, meanwhile, the lateral insulating layer exhibits the unique width effect on the leakage current and the circuit speed of the device, establishes the model for this effect, and provides relevant design guidelines. In addition, a new type of channel doping design, called SCD, is discussed. A DG device using SCD provides a good balance between bounce mode and threshold control. Finally, the guidelines for making a SADG MOSFET are summarized