【摘 要】
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On the basis of analyzing CCD signals timing and star image processing, a new design and a special parallel architecture for improving star image processing are
【机 构】
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School of Electricity and Information Engineering,School of Mathematics and Computer Science
论文部分内容阅读
On the basis of analyzing CCD signals timing and star image processing, a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design, the operation moving the data in expanded windows, including the star, to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. While the CCD saves the star image to memory, DSP processes the data in the onchip memory. This parallelism greatly improves the efficiency of processing. DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The five lightest stars in the star acquisition stage are acquired in only 3. 5 ms. In 43 μs, the data in five expanded windows including stars are moved into the internal memory of DSP, and in 1.6 ms, five star coordinates are achieved in the star tracking stage.
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