论文部分内容阅读
提出了一个求解ＦＰＧＡ延时／面积最小化工艺映射分层序列法。它首先给出了求解延时最小化工艺映射的步骤；然后在不增加延时的情况下，进行面积最小化．
A solution to FPGA delay / area minimization process mapping hierarchical sequence method is proposed. It first gives the steps to solve the delay-minimization process map, and then minimizes the area without increasing the delay.