We present a novel standard convolutional symbols generator (SCSG) block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption ofmultiple parameters. The SCSG block generates all the states and calculates all the possiblestandard convolutional symbols corresponding to thestates using an iterative approach. The ar-chitecture of the Viterbi decoder based on the SCSG reducesresource consumptionfor recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths. The proposed architecture supports constraint lengths from 3 to 9, code rates of 1/2, 1/3, and1/4, and fully optional polynomials. The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200Mbps and a low resource consumption of 162k logic gates.