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基于低压差分信号比较器的结构,研究了影响比较器输出抖动的各种因素,并指出:根据差分信号的输入摆幅来优化电路有助于降低电路的输出抖动。基于0.13μm CMOS工艺,优化设计了一种低抖动的低压差分信号比较器电路。仿真结果显示,该低压差分信号比较器电路能够转换传输速率高达4Gb/s的信号,在输入信号差分摆幅确定的条件下,其额外引入的峰峰值抖动为2ps。
Based on the structure of the low-voltage differential signal comparator, various factors that affect the output jitter of the comparator are investigated. It is pointed out that optimizing the circuit based on the input swing of the differential signal can reduce the output jitter of the circuit. Based on the 0.13μm CMOS process, a low-jitter low-voltage differential signal comparator circuit is optimized. The simulation results show that the low-voltage differential signal comparator circuit can convert the signals with the transmission rate up to 4 Gb / s, and the additional peak-to-peak jitter is 2 ps when the input signal differential swing is determined.