Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InGaP barrier layer and Al_2 O_3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current I_d-V_g measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △V_g in the oncurrent region. The I_d-V_g degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically; the stress induced acceptor traps contain both permanent and recoverable traps. Compared with surface channel InGaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones. Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InGaP barrier layer and Al_2 O_3 dielectric is investigated. Well behaved split CV characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current I_d-V_g measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and the degradation of positive ΔV_g in the oncurrent region. The I_d-V_g degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. channel ones.